In recent years, in accordance with the requests of size reduction, high performance, and cost reduction of electronic devices, the miniaturization and multilayering of a circuit board with semiconductor chips mounted thereon, and the high density mounting of electronic components on the circuit board have been advanced along with the miniaturization and increase in terminals of each of the semiconductor chips.
Circuit boards have been diversified into various kinds and have become complicated. As represented by a pseudo system on chip (SOC) technique, there has been studied a technique which integrally forms a circuit by using a substrate that is formed by sealing with resin a plurality of semiconductor chips having different characteristics. In the pseudo SOC technique, a rewiring layer, which includes a wiring portion, and the like, for electrically connecting the adjacent semiconductor chips to each other, is formed on a reconstructed wafer with the plurality of semiconductor chips embedded therein.
Various techniques have been developed as techniques for forming a pattern of a metallic material.    Patent Document 1: Japanese Laid-Open Patent Publication No. 2009-64954    Patent Document 2: Japanese Patent No. 4543089    Patent Document 3: Japanese Laid-Open Patent Publication No. 2001-351923